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2M x 8-Bit Dynamic RAM
HYB3117800BSJ-50/-60/-70
Advanced Information
* * *
2 097 152 words by 8-bit organization 0 to 70 C operating temperature Performance: -50 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 90 35 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns
* *
Single + 3.3 V ( 0.3V) supply Low power dissipation max. 432 active mW (-50 version) max. 396 active mW (-60 version) max. 360 active mW (-70 version) 7.2 mW standby (LV-TTL) 3.6 mW standby (CMOS) Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh and test mode Fast page mode capability All inputs, outputs and clocks fully LVTTL-compatible 2048 refresh cycles / 32 ms Plastic Package: P-SOJ-28-3 400 mil
* *
* * * *
Semiconductor Group
1
1.96
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
The HYB 3117800BSJ is a 16 MBit dynamic RAM organized as 2097152 words by 8-bits. The HYB 3117800BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 3117800BSJ to be packaged in a standard SOJ 28 400 mil plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 3.3 V ( 0.3V) power supply, direct interfacing with high-performance logic device families. Ordering Information Type HYB 3117800BSJ-50 HYB 3117800BSJ-60 HYB 3117800BSJ-70 Pin Names A0 to A10 A0 to A9 RAS OE I/O1-I/O8 CAS WE Row Address Inputs Column Address Inputs Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply (+ 3.3 V) Ground (0 V) not connected Ordering Code Q67100-Q1147 Q67100-Q1148 Package P-SOJ-28-3 P-SOJ-28-3 P-SOJ-28-3 400 mil 400 mil 400 mil Descriptions
3.3V DRAM (access time 50 ns) 3.3V DRAM (access time 60 ns) 3.3V DRAM (access time 70 ns)
VCC VSS
N.C.
Semiconductor Group
2
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
P-SOJ-28-3 (400mil)
VCC I/O1 I/O2 I/O3 I/O4 WE RAS N.C. A10 A0 A1 A2 A3 VCC
O 1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS I/O8 I/O7 I/O6 I/O5 CAS OE A9 A8 A7 A6 A5 A4 VSS
Pin Configuration
Semiconductor Group
3
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
I/O1 I/O2
I/O8
WE CAS
.
&
Data in Buffer
No. 2 Clock Generator 8
Data out Buffer
8
OE
10
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
11
Column Address Buffer(10)
10
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
8
Refresh Counter (11) 11 Row
1024 x8
Address Buffers(11)
11
Decoder 2048
Row
Memory Array 2048x1024x8
RAS
No. 1 Clock
Generator
Block Diagram
Semiconductor Group
4
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 C Storage temperature range.........................................................................................- 55 to 150 C Input/output voltage ...............................................................................-0.5 to min (Vcc+0.5, 4.6) V Power supply voltage...................................................................................................-1.0V to 4.6 V Power dissipation..................................................................................................................... 0.5 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3V, tT = 5 ns Parameter Input high voltage Input low voltage LVTTL Output high voltage (IOUT = -2 mA) LVTTL Output low voltage (IOUT = 2 mA) CMOS Output high voltage (IOUT = -100 A) CMOS Output low voltage (IOUT = 100 A) Input leakage current,any input (0 V VIH Vcc + 0.3V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V VOUT Vcc + 0.3V) Average VCC supply current: -50 ns version -60 ns version -70 ns version (RAS, CAS, address cycling, tRC = tRC min.) Symbol Limit Values min. max. Vcc+0.5 0.8 - 0.4 - 0.2 10 10 2.0 - 0.5 2.4 - Vcc-0.2 - - 10 - 10 Unit Test Condition V V V V V V A A ) 1) 1) 1) 1) 1) 1)
VIH VIL VOH VOL VOH VOL II(L) IO(L) ICC1
- - - - - - -
120 110 100 2 120 110 100
mA mA mA mA mA mA mA
2) 3) 4) 2) 3) 4) 2) 3) 4)
Standby VCC supply current (RAS = CAS = VIH) ICC2
Average VCC supply current, during RAS-only refresh cycles: -50 ns version -60 ns version -70 ns version (RAS cycling: CAS = VIH, tRC = tRC min.)
-
2) 4) 2) 4) 2) 4)
ICC3
Semiconductor Group
5
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
DC Characteristics (cont'd) TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3V, tT = 5 ns Parameter Symbol Limit Values min. Average VCC supply current, ICC4 during fast page mode: -50 ns version -60 ns version -70 ns version (RAS = VIL, CAS, address cycling,tPC = tPC min.) - - - - max. 40 35 30 1 Unit Test Condition mA mA mA mA
2) 3) 4) 2) 3) 4) 2) 3) 4)
Standby VCC supply current (RAS = CAS = VCC - 0.2 V)
Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version -60 ns version -70 ns version (RAS, CAS cycling, tRC = tRC min.)
ICC5 ICC6
1)
- - -
120 110 100
mA mA mA
2) 4) 2) 4) 2) 4)
Average Self Refresh Current
(CBR cycle with tRAS>TRASSmin., CAS held low, WE=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
ICC7
_
1
mA
Capacitance TA = 0 to 70 C,VCC = 3.3 V 0.3V, f = 1 MHz Parameter Input capacitance (A0 to A10) Input capacitance (RAS, CAS, WE, OE) I/O capacitance (I/O1-I/O8) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
Semiconductor Group
6
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3 V, tT = 5 ns Parameter
Symbol
16F
Limit Values -50 min. -60 -70 max. - - 10k 10k - - - - 50 35 - - - 50 32 max. min. - - 10k 10k - - - - 37 25 110 40 60 15 0 10 0 15 20 15 15 60 - 50 32 5 3 - max. min. - - 10k 10k - - - - 45 30 - - - 50 32 130 50 70 20 0 10 0 15 20 15 20 70 5 3 -
Unit Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 90 30 50 13 0 8 0 10 18 13 13 50 5 3 - ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7
Read Cycle
Access time from RAS Access time from CAS OE access time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay tRAC tCAC tOEA tRCS tRCH tRRH tCLZ tOFF - - - - 25 0 0 0 0 0 50 13 25 13 - - - - - 13 - - - - 30 0 0 0 0 0 60 15 30 15 - - - - - 15 - - - - 35 0 0 0 0 0 70 20 35 20 - - - - - 20 ns ns ns ns ns ns ns ns ns ns 11 11 8 12 8, 9 8, 9 8,10
Access time from column address tAA Column address to RAS lead time tRAL
Semiconductor Group
7
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3 V, tT = 5 ns Parameter
Symbol
16F
Limit Values -50 min. -60 0 0 15 15 15 - - - 0 0 20 20 -70 max. 20 - - - max. min. 13 - - - max. min.
Unit Note
Output buffer turn-off delay from OE Data to OE low delay CAS high to data delay OE high to data delay
tOEZ tDZO tCDD tODD
0 0 13 13
ns ns ns ns
12 13 14 14
Write Cycle
Write command hold time Write command pulse width Write command setup time tWCH tWP tWCS 8 8 0 13 13 0 10 0 - - - - - - - - 10 10 0 15 15 0 10 0 - - - - - - - - 10 10 0 20 20 0 15 0 - - - - - - - - ns ns ns ns ns ns ns ns 16 16 13 15
Write command to RAS lead time tRWL Write command to CAS lead time tCWL Data setup time Data hold time Data to CAS low delay tDS tDH tDZC
Read-Modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time OE command hold time tRWC tRWD tCWD tOEH 126 68 31 43 13 - - - - - 150 80 35 50 15 - - - - - 180 95 45 60 20 - - - - - ns ns ns ns ns 15 15 15
Column address to WE delay time tAWD
Fast Page Mode Cycle
Fast page mode cycle time CAS precharge time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay tPC tCP tCPA tRAS tRHPC 35 10 - 50 30 - - 30 - 40 10 - 35 - - 35 - 45 10 - 40 - - 40 - ns ns ns ns 7
200k 60
200k 70
200k ns
Semiconductor Group
8
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3 V, tT = 5 ns Parameter
Symbol
16F
Limit Values -50 min. -60 -70 max. - - max. min. - - 80 55 max. min. - - 95 65
Unit Note
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle time CAS precharge to WE tPRWC tCPWD 71 48 ns ns
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time tCSR tCHR tRPC tWRP 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns
Write hold time referenced to RAS tWRH
CAS-before-RAS Counter Test Cycle
CAS precharge time tCPT 35 - 40 - 40 - ns
Test Mode
CAS hold time Write command setup time Write command hold time tCHRT tWTS tWTH 30 10 10 - - - 30 10 10 - - - 30 10 10 - - - ns ns ns
Self Refresh Cycle
RAS pulse width RAS precharge time CAS hold time tRASS tRPS tCHS 100k - 95 -50 - - 100k - 110 -50 - - 100k - 130 -50 - - ns ns ns 17 17 17
Semiconductor Group
9
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
Notes:
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 100 pF and at Voh=2.0 V (Ioh = -2mA) , Vol=0.8V (Iol=2mA). 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13)Either tDZC or tDZO must be satisfied. 14)Either tCDD or tODD must be satisfied. 15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh.
Semiconductor Group
10
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
V IH
CAS
VIL
tRAD tASR tASC tCAH
Column
tASR
Row
Address
V IH VIL
Row
tRCH tRAH tRCS tRRH tAA tOEA
V
WE
IH
VIL
OE
V IH VIL
tDZC tDZO tODD tCAC tCLZ
Hi Z
tCDD
I/O (Inputs)
V
IH
VIL
tOFF tOEZ
Valid Data Out Hi Z
I/O (Outputs) V
V OH OL
tRAC
"H" or "L"
WL1
Read Cycle
Semiconductor Group
11
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL tCAH
Column
tCRP
V IH
CAS
VIL
tRAD tASR tASC
tASR
Row
Address
V IH VIL
.
Row
tRAH
V
tWCS t WP
tCWL
WE
IH
VIL
tWCH tRWL
OE
V IH VIL
tDS
I/O (Inputs)
V IH VIL
tDH
Valid Data In
OH I/O (Outputs) V OL
V
Hi Z
"H" or "L"
WL2
Write Cycle (Early Write)
Semiconductor Group
12
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V
IH
CAS
VIL
tRAD tASR tASC tCAH
Column
tASR
. Row
V
IH
Address V IL
Row
tRAH
V
WE
IH
tCWL tRWL tWP
VIL
tOEH
V
OE
IH
VIL
tDZO tDZC
I/O (Inputs)
V IH VIL
tODD tDS tOEZ tCLZ tOEA
tDH
Valid Data
OH I/O (Outputs) V OL
V
Hi-Z
Hi-Z
"H" or "L"
WL3
Write Cycle (OE Controlled Write)
Semiconductor Group
13
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
tRWC tRAS
V IH VIL V IH
tRP
RAS
tCSH tRCD tRSH tCAS tCRP
CAS
VIL
tRAH tASR
V
tCAH tASC
Column
tASR
Row
Address
IH
VIL
Row
tRAD
V
tAWD tCWD tRWD
tCWL tRWL tWP
IH
WE
VIL
tAA tRCS
V IH
tOEA
tOEH
OE
VIL
tDZO tDZC
I/O (Inputs)
V IH VIL
tDS tDH
Valid Data in
tCLZ tCAC
tODD tOEZ
Data Out
I/O (Outputs) V OL
V OH
tRAC
"H" or "L"
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
14
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
tRASP
V IH
tRP
RAS
VIL
tPC tRCD
V IH
tCAS
tCP
tCAS
tRHCP tRSH tCAS
tCRP
CAS
VIL
tCSH tRAH tASR tASC tCAH
Column
tASC
tCAH tASC
tCAH tASR
Row Column
V
Address
IH
Row
Column
VIL
tRAD tRCH tRCS tRCS tRCS
tRCH
V IH
WE
VIL
tAA
V IH
tCPA tAA tOEA
tOEA
tCPA tAA tOEA tDZC tODD tDZO
tRRH
OE
VIL
tDZC tDZO tODD
tDZC tDZO
tCDD tODD
I/O (Inputs)
V
IH
VIL
tCAC tRAC tCLZ
tOFF tOEZ
Valid Data Out
tCAC tCLZ
tOFF tOEZ
Valid Data Out
tCAC tCLZ
tOFF tOEZ
Valid Data Out
OH I/O (Outputs) V OL
V
"H" or "L"
FPM1
Fast Page Mode Read Cycle Semiconductor Group 15
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
tRAS
V IH
tRP
RAS
VIL
tPC tRCD
V IH
tRSH tCP tCAS tCAS tCRP
tCAS
CAS
VIL
tRAH tASR
V
tRAL tCAH tASC tASC
Column Column
tCAH tASC
tCAH
tASR
Column
Address
IH Row
VIL
Column
tRAD tWCS
V
tCWL tWCH tWP
tWCS
tCWL tWCH tWP
tWCS
tCWL tRWL tWCH tWP
WE
IH
VIL
OE
V IH VIL
tDH tDS
I/O (Inputs)
V IH VIL Valid Data In
tDH tDS
Valid Data In
tDH tDS
Valid Data In
OH I/O (Outputs) V OL
V
HI-Z
"H" or "L"
FPM2
Fast Page Mode Early Write Cycle
Semiconductor Group
16
tRAS tRP
V
RAS
IH
V IL
tCSH tPRWC tCAS tCP tCAS tCRP tCAS tRSH tRCD
Semiconductor Group
V
CAS
IH
V IL
tRAD tCAH tASC tASC
Column Column Column Address
tASR tASC
tRAH
tCAH tCAH
tRAL tASR
Row
V
Address
IH
V IL
Row
tRCS tCWL tCWL tAWD tWP tOEA tOEA tAWD tWP tAWD tAA tOEA
tRWD tCWD tCPWD tCWD
tCPWD tCWD
Fast Page Mode Read-Modify-Write Cycle
V
tRWL tCWL tWP
WE
IH
V IL
17
V
IH
OE
V IL
V
Data In
IH
tDZC tCLZ tDZO tODD
Data In
tCPA tDZC tCLZ
tCPA tDZC tCLZ tOEH tCAC tOEZ tDS
Data Out Data Out
tODD
Data In
I/O (Inputs) V IL
tCAC tRAC tOEZ tDH tDS
Data Out
tODD tAA
tOEH
tOEH tDH tAA tOEZ tDS tDH
OH I/O (Outputs) V
V
OL
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
"H" or "L"
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCRP tRPC
CAS
V IH VIL
tRAH tASR
tASR
Row
V
Address
IH
VIL
Row
OH I/O (Outputs) V OL
V
HI-Z
"H" or "L"
WL9
RAS-Only Refresh Cycle
Semiconductor Group
18
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
tRC tRP
V
tRAS
tRP
RAS
IH
VIL
tRPC tCP
tCSR tCHR tRPC
tCRP
CAS
V IH VIL
tWRP tWRH
V IH
WE
VIL
tOEZ
V
OE
IH
VIL
tCDD
I/O (Inputs)
V IH
VIL
tODD
OH I/O (Outputs)VOL V
HI-Z
tOFF
"H" or "L"
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
19
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
tRC
V
tRC tRP tRAS tRP
tRAS
IH
RAS
VIL
tRCD
V
tRSH tCHR tCRP
CAS
IH
VIL
tRAD tASC tASR tRAH
Row
tWRP tCAH tWRH tASR
Row
V
Address
IH
VIL
Column
tRCS
V
tRRH
WE
IH
VIL
tAA tOEA
V
OE
IH
VIL
tDZC tDZO
tCDD tODD tCAC tCLZ
V
I/O (Inputs)
IH
VIL
tOFF tOEZ
Valid Data Out HI-Z
tRAC
OH I/O (Outputs) V OL V
"H" or "L"
WL11
Hidden Refresh Cycle (Read) Cycle
Semiconductor Group
20
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
tRC tRP
V IH
tRC tRP tRAS
tRAS
RAS
VIL
tRCD
V IH
tRSH
tCHR
tCRP
CAS
VIL
tRAD tRAH tASR tASC tCAH
Column
tASR
Row
V
Address
IH
VIL
Row
tWCS
tWCH tWP
tWRP
tWRH
V
WE
IH
VIL
tDS
V
tDH
Valid Data
I/O (Input)
IH
V IL
OH I/O (Output) V OL
V
HI-Z
"H" or "L"
WL12
Hidden Refresh Cycle (Early Write)
Semiconductor Group
21
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
tRP
RAS
V IH VIL
tRASS
tRPS
tRPC tCSR
V
tCHS
tCRP
tCP
IH
CAS
VIL
tWRP tWRH
V
WE
IH
VIL
OE
V IH VIL
tCDD
I/O (Inputs)
V IH
VIL
tODD tOEZ
OH I/O (Outputs) V OL
V
HI-Z
tOFF
"H" or "L"
WL13
CAS before RAS Self Refresh Cycle
Semiconductor Group
22
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
tRAS
Read Cycle:
RAS
V IH V IL
tRP
tCSR
CAS
V IH V IL
tCHR
tCP
tRSH tCAS tRAL
tASC
Address
V IH V IL
tCAH tAA tCAC
tASR
Row
Column
tWRP
WE
V IH V IL V IH V IL V IH V IL VOH VOL
tRRH tOEA tCDD tOFF tOEZ
Data Out
tRCH
tWRH
tRCS tDZC tDZO tCLZ
OE I/O (Inputs)
tODD
I/O (Outputs)
tWRP
Write Cycle:
WE
V IH V IL
tWCS
tRWL tCWL tWCH
tWRH
OE
V IH V IL
tDS
I/O (Inputs) I/O (Outputs)
V IH V IL V IH V IL
tDH
Data In
HI-Z
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
23
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
tRP
V
tRC tRAS tRP
RAS
IH
VIL
tRPC tCP tCSR tCHR tRPC tCRP
V
CAS
IH
VIL
tASR tRAH
Address IH
VIL V
Row
tWTS
V
tWTH
WE
IH
VIL
V
OE
IH
VIL
I/O IH (Inputs) V IL
V
tODD
HI-Z
tCDD tOEZ
I/O (Outputs) V
V OH OL
HI-Z
tOFF
"H" or "L"
WL15
Test Mode Entry
Semiconductor Group
24
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
Test Mode As the HYB 3117800BSJ is organized internally as 1M x 16-bits, a test mode cycle using 2:1 compression can be used to improve test time. Note that in the 2M x 8 version the test time is reduced by 1/2 for a N test pattern. In a test mode "write" the data from each I/O pin is written into two 1M blocks simultaneously (all "1" s or all "0" s). In test mode "read" each I/O output is used for indicating the test mode result. If the internal two bits are equal, the I/O would indicate a "1". If they were not equal, the I/O would indicate a "0". The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit from test mode, a "CAS before RAS refresh", "RAS only refresh" or "Hidden refresh" can be used. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cylces. Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other addresses are don't care.
Semiconductor Group
25
HYB 3117800BSJ-50/-60/-70 2M x 8-DRAM
Package Outlines
Plastic Package P-SOJ-28-3 (400 mil) (Small Outline J-lead, SMD)
10.16
1) +0.13
-
30
O
1.27 0.51 -0.13
0.81max
9.4 0.1 11.18
+ 0.25
-
0.18
M
28x
0.18
+0.13 -
M
GPJ05699
28
15
1 18.54
1) -0.25
14
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
Semiconductor Group
26

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